SherbyNet - /page/wikibook/entry.mu

Micron Document

`:top

In `F33f`_`[computer architecture`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Computer_architecture]`_`f, `!128-bit`! `F33f`_`[integers`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Integer_(computer_science)]`_`f, `F33f`_`[memory addresses`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Memory_address]`_`f, or other `F33f`_`[data`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Data_(computing)]`_`f units are those that are 128 `F33f`_`[bits`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Bit]`_`f (16 `F33f`_`[octets`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Octet_(computing)]`_`f) wide. Also, 128-bit `F33f`_`[central processing unit`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Central_processing_unit]`_`f (CPU) and `F33f`_`[arithmetic logic unit`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Arithmetic_logic_unit]`_`f (ALU) architectures are those that are based on `F33f`_`[registers`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Processor_register]`_`f, `F33f`_`[address buses`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Address_bus]`_`f, or `F33f`_`[data buses`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Bus_(computing)]`_`f of that size.

As of July 2025 there are currently no mainstream `F33f`_`[general-purpose processors`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=History_of_general-purpose_CPUs]`_`f built to operate on 128-bit `*integers`* or addresses, although a number of processors do have specialized ways to operate on 128-bit chunks of data as summarized in `F33f`_`[§ Hardware`#hardware]`_`f.

>>Contents

• `F0af`_`[Representation`#representation]`_`f

• `F0af`_`[Hardware`#hardware]`_`f

• `F0af`_`[Software`#software]`_`f

• `F0af`_`[Other uses`#other-uses]`_`f

• `F0af`_`[References`#references]`_`f

-─

>>Representation

A processor with 128-bit byte addressing could directly address up to 2128 (over 3.40×1038) bytes, which would greatly exceed the total data captured, created, or replicated on Earth as of 2018, which has been estimated to be around 33 `F33f`_`[zettabytes`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Zettabyte]`_`f (over 274 bytes).`:cite-ref-1[`F5bf`_`[1`#cite-note-1]`_`f]

A 128-bit register can store 2128 (over 3.40 × 1038) different values. The range of `F33f`_`[integer`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Integer]`_`f values that can be stored in 128 bits depends on the `F33f`_`[integer representation`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Integer_(computer_science)]`_`f used. With the two most common representations, the range is 0 through 340,282,366,920,938,463,463,374,607,431,768,211,455 (2128 − 1) for representation as an (`F33f`_`[unsigned`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Signedness]`_`f) `F33f`_`[binary number`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Binary_number]`_`f, and −170,141,183,460,469,231,731,687,303,715,884,105,728 (−2127) through 170,141,183,460,469,231,731,687,303,715,884,105,727 (2127 − 1) for representation as `F33f`_`[two's complement`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Two's_complement]`_`f.

Quadruple precision (128 bits) floating-point numbers can store 113-bit `F33f`_`[fixed-point`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Fixed-point_arithmetic]`_`f numbers or `F33f`_`[integers`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Integer_(computer_science)]`_`f accurately without losing `F33f`_`[precision`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Precision_(computer_science)]`_`f (thus 64-bit integers in particular). Quadruple precision floats can also represent any position in the `F33f`_`[observable universe`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Observable_universe]`_`f with at least micrometer precision.

Decimal128 floating-point numbers can represent numbers with up to 34 significant digits.

>>Hardware

A 128-bit `F33f`_`[multicomparator`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Multicomparator]`_`f was described by researchers in 1976.`:cite-ref-2[`F5bf`_`[2`#cite-note-2]`_`f]

The `F33f`_`[IBM System/360 Model 85`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IBM_System/360_Model_85]`_`f,`:cite-ref-3[`F5bf`_`[3`#cite-note-3]`_`f] and `F33f`_`[IBM System/370`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IBM_System/370]`_`f and its successors, support 128-bit floating-point arithmetic.

The `F33f`_`[Siemens`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Siemens]`_`f 7.700 and 7.500 series mainframes and their successors support 128-bit floating-point arithmetic.`:cite-ref-4[`F5bf`_`[4`#cite-note-4]`_`f]

Most modern CPUs feature `F33f`_`[single instruction, multiple data`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Single_instruction,_multiple_data]`_`f (SIMD) instruction sets (`F33f`_`[Streaming SIMD Extensions`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Streaming_SIMD_Extensions]`_`f, `F33f`_`[AltiVec`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=AltiVec]`_`f etc.) where 128-bit `F33f`_`[vector registers`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Vector_registers]`_`f are used to store several smaller numbers, such as four 32-bit floating-point numbers. A single instruction can then operate on all these values in parallel. However, these processors do not operate on individual numbers that are 128 binary digits in length; only their vector registers have the size of 128 bits.

The DEC `F33f`_`[VAX`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=VAX]`_`f supported operations on 128-bit integer ('O' or octaword) and 128-bit floating-point ('H-float' or HFLOAT) datatypes. Support for such operations was an upgrade option rather than being a standard feature. Since the VAX's registers were 32 bits wide, a 128-bit operation used four consecutive registers or four longwords in memory.

The `F33f`_`[ICL 2900 Series`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=ICL_2900_Series]`_`f provided a 128-bit accumulator, and its instruction set included 128-bit floating-point and `F33f`_`[packed decimal`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Packed_decimal]`_`f arithmetic.

A CPU with 128-bit multimedia extensions was designed by researchers in 1999.`:cite-ref-5[`F5bf`_`[5`#cite-note-5]`_`f]

Among the `F33f`_`[sixth generation of video game consoles`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Sixth_generation_of_video_game_consoles]`_`f, the `F33f`_`[Dreamcast`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Dreamcast]`_`f and the `F33f`_`[PlayStation 2`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=PlayStation_2]`_`f used the term `*128-bit`* in their marketing to describe their capability. The Playstation 2's CPU had 128-bit SIMD capabilities.`:cite-ref-caaqa-6-0[`F5bf`_`[6`#cite-note-caaqa-6]`_`f]`:cite-ref-mpr-7-0[`F5bf`_`[7`#cite-note-mpr-7]`_`f] Neither console supported 128-bit addressing or 128-bit integer arithmetic.

The `F33f`_`[RISC-V`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=RISC-V]`_`f ISA specification from 2016 includes a reservation for a 128-bit version of the architecture, but the details remain undefined intentionally, because there is yet so little practical experience with such large word size.`:cite-ref-isa-8-0[`F5bf`_`[8`#cite-note-isa-8]`_`f]

>>Software

In the same way that `F33f`_`[compilers`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Compiler]`_`f emulate, e.g., 64-bit integer arithmetic on architectures with register sizes less than 64 bits, some compilers also support 128-bit integer arithmetic. For example, the `F33f`_`[GCC C compiler`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=GNU_Compiler_Collection]`_`f 4.6 and later has a 128-bit integer type `B100`F9d9__int128`f`b for some architectures.`:cite-ref-9[`F5bf`_`[9`#cite-note-9]`_`f] GCC and compatible compilers signal the presence of 128-bit arithmetic when the macro `B100`F9d9__SIZEOF_INT128__`f`b is defined.`:cite-ref-10[`F5bf`_`[10`#cite-note-10]`_`f] For the `F33f`_`[C programming language`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=C_programming_language]`_`f, 128-bit support is optional, e.g. via the `B100`F9d9int128_t`f`b type, or it can be implemented by a compiler-specific extension. The `F33f`_`[Rust`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Rust_(programming_language)]`_`f programming language has built-in support for 128-bit integers (originally via `F33f`_`[LLVM`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=LLVM]`_`f), which is implemented on all platforms.`:cite-ref-11[`F5bf`_`[11`#cite-note-11]`_`f] A 128-bit type provided by a C compiler can be available in `F33f`_`[Perl`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Perl]`_`f via the `B100`F9d9Math::Int128`f`b module.`:cite-ref-12[`F5bf`_`[12`#cite-note-12]`_`f]

>>>Other uses

• `F33f`_`[Universally unique identifiers`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Universally_unique_identifier]`_`f (UUID) consist of a 128-bit value.

• `F33f`_`[IPv6`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IPv6]`_`f routes computer network traffic amongst a 128-bit range of addresses.

• `F33f`_`[ZFS`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=ZFS]`_`f is a 128-bit file system.

• 128 bits is a common `F33f`_`[key size`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Key_size]`_`f for `F33f`_`[symmetric ciphers`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Symmetric_cipher]`_`f and a common block size for `F33f`_`[block ciphers`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Block_cipher]`_`f in `F33f`_`[cryptography`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Cryptography]`_`f.

• The `F33f`_`[IBM i`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IBM_i]`_`f Machine Interface defines all pointers as 128-bit. The Machine Interface instructions are translated to the hardware's real instruction set as required, allowing the underlying hardware to change without needing to recompile the software. Past hardware had a `F33f`_`[CISC`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Complex_instruction_set_computer]`_`f instruction set with 48-bit addressing, while current hardware is 64-bit `F33f`_`[PowerPC`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=PowerPC]`_`f/`F33f`_`[Power ISA`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Power_ISA]`_`f. In the PowerPC/Power ISA implementation, the first four bytes contain information used to identify the type of the object being referenced, and the final eight bytes are used as a virtual memory address.`:cite-ref-inside-as400-13-0[`F5bf`_`[13`#cite-note-inside-as400-13]`_`f] The remaining four bytes are unused, and would allow IBM i applications to be extended to 96-bit addressing in future without requiring code changes.

• Increasing the word size can speed up `F33f`_`[multiple precision`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Arbitrary-precision_arithmetic]`_`f mathematical libraries, with applications to `F33f`_`[cryptography`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Cryptography]`_`f, and potentially speed up algorithms used in complex mathematical processing (`F33f`_`[numerical analysis`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Numerical_analysis]`_`f, `F33f`_`[signal processing`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Signal_processing]`_`f, complex `F33f`_`[photo editing`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Photo_manipulation]`_`f and `F33f`_`[audio`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Audio_signal_processing]`_`f and `F33f`_`[video processing`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Video_processing]`_`f).

• `F33f`_`[MD5`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=MD5]`_`f is a hash function producing a 128-bit hash value.

• `F33f`_`[Apache Avro`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Apache_Avro]`_`f uses a 128-bit random number as synchronization marker for efficient splitting of data files.`:cite-ref-14[`F5bf`_`[14`#cite-note-14]`_`f]`:cite-ref-15[`F5bf`_`[15`#cite-note-15]`_`f]

>>References

`:cite-note-1`!1.`! `F0af`_`[↑`#cite-ref-1]`_`f `:citerefreinselgantzrydning2018`aReinsel, David; Gantz, John; Rydning, John (November 2018). "The Digitalization of the World from Edge to Core" (PDF). `*`F33f`_`[Seagate Technology`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Seagate_Technology]`_`f`*. `F33f`_`[IDC`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=International_Data_Corporation]`_`f. p. 3. Archived (PDF) from the original on 7 September 2021. Retrieved 14 September 2021.

`:cite-note-2`!2.`! `F0af`_`[↑`#cite-ref-2]`_`f `:citerefmeadpashleybrittondaimon1976`a`F33f`_`[Mead, Carver A.`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Carver_Mead]`_`f; Pashley, Richard D.; Britton, Lee D.; Daimon, Yoshiaki T.; Sando, Stewart F. Jr. (October 1976). "128-Bit Multicomparator" (PDF). `*`F33f`_`[IEEE Journal of Solid-State Circuits`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IEEE_Journal_of_Solid-State_Circuits]`_`f`*. `!11`! (5): 692–695. `F33f`_`[Bibcode`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Bibcode_(identifier)]`_`f:1976IJSSC..11..692M. `F33f`_`[doi`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Doi_(identifier)]`_`f:10.1109/JSSC.1976.1050799. `F33f`_`[S2CID`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=S2CID_(identifier)]`_`f 27262034. Archived (PDF) from the original on 3 November 2018.

`:cite-note-3`!3.`! `F0af`_`[↑`#cite-ref-3]`_`f `:citerefpadegs-a1968`aPadegs A (1968). "Structural aspects of the System/360 Model 85, III: Extensions to floating-point architecture". `*IBM Systems Journal`*. `!7`!: 22–29. `F33f`_`[doi`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Doi_(identifier)]`_`f:10.1147/sj.71.0022.

`:cite-note-4`!4.`! `F0af`_`[↑`#cite-ref-4]`_`f `*Assembler Instructions (BS2000/OSD)`*. 1993.

`:cite-note-5`!5.`! `F0af`_`[↑`#cite-ref-5]`_`f `:citerefsuzuokikutaragihiroimagoshi1999`aSuzuoki, M.; Kutaragi, K.; Hiroi, T.; Magoshi, H.; Okamoto, S.; Oka, M.; Ohba, A.; Yamamoto, Y.; Furuhashi, M.; Tanaka, M.; Yutaka, T.; Okada, T.; Nagamatsu, M.; Urakawa, Y.; Funyu, M.; Kunimatsu, A.; Goto, H.; Hashimoto, K.; Ide, N.; Murakami, H.; Ohtaguro, Y.; Aono, A. (November 1999). "A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder". `*`F33f`_`[IEEE Journal of Solid-State Circuits`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=IEEE_Journal_of_Solid-State_Circuits]`_`f`*. `!34`! (11): 1608–1618. `F33f`_`[Bibcode`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Bibcode_(identifier)]`_`f:1999IJSSC..34.1608S. `F33f`_`[doi`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Doi_(identifier)]`_`f:10.1109/4.799870.

`:cite-note-caaqa-6`!6.`! `F0af`_`[↑`#cite-ref-caaqa-6-0]`_`f `:citerefhennessypatterson2003`a`F33f`_`[Hennessy, John L.`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=John_L._Hennessy]`_`f; `F33f`_`[Patterson, David A.`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=David_Patterson_(scientist)]`_`f (2003). `*Computer Architecture: A Quantitative Approach`* (Third ed.). Morgan Kaufmann Publishers. `F33f`_`[ISBN`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=ISBN_(identifier)]`_`f 1-55860-724-2.

`:cite-note-mpr-7`!7.`! `F0af`_`[↑`#cite-ref-mpr-7-0]`_`f `:citerefdiefendorff1999`a`F33f`_`[Diefendorff, Keith`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Keith_Diefendorff]`_`f (19 April 1999). "Sony's Emotionally Charged Chip". `*`F33f`_`[Microprocessor Report`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Microprocessor_Report]`_`f`*. `!13`! (5). Microdesign Resources.

`:cite-note-isa-8`!8.`! `F0af`_`[↑`#cite-ref-isa-8-0]`_`f `:citerefwatermanasanovi`aWaterman, Andrew; `F33f`_`[Asanović, Krste`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Krste_Asanović]`_`f. "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.2". University of California, Berkeley. EECS-2016-118. Retrieved 25 May 2017.

`:cite-note-9`!9.`! `F0af`_`[↑`#cite-ref-9]`_`f "GCC 4.6 Release Series – Changes, New Features, and Fixes". Retrieved 25 July 2016.

`:cite-note-10`!10.`! `F0af`_`[↑`#cite-ref-10]`_`f `:citerefmarc-glisse2015`aMarc Glisse (26 August 2015). "128-bit integer – nonsensical documentation?". GCC-Help. Retrieved 23 January 2020.

`:cite-note-11`!11.`! `F0af`_`[↑`#cite-ref-11]`_`f "i128 – Rust". `*doc.rust-lang.org`*. Retrieved 25 June 2020.

`:cite-note-12`!12.`! `F0af`_`[↑`#cite-ref-12]`_`f "Math::Int128". `*metacpan.org`*. Retrieved 25 June 2020.

`:cite-note-inside-as400-13`!13.`! `F0af`_`[↑`#cite-ref-inside-as400-13-0]`_`f `:citereffrank-g-soltis1997`aFrank G. Soltis (1997). `*Inside the AS/400, Second Edition`*. Duke Press. `F33f`_`[ISBN`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=ISBN_(identifier)]`_`f 978-1-882419-66-1.

`:cite-note-14`!14.`! `F0af`_`[↑`#cite-ref-14]`_`f `:citerefkleppmann2013`aKleppmann, Martin (24 January 2013). "Re: Synchronization Markers". Archived from the original on 27 September 2015.

`:cite-note-15`!15.`! `F0af`_`[↑`#cite-ref-15]`_`f "Apache Avro 1.8.0 Specification". `F33f`_`[Apache Software Foundation`:/page/wikibook/entry.mu`zim=wikipedia_en_all_nopic_2025-08.zim|entry_path=Apache_Software_Foundation]`_`f.

`c`F0af`_`[↑ Back to top`#top]`_`f`a